Writing ASIC source files in Verilog Hardware Description Language, (Verilog HDL), requires certain redundant overhead. The redundant overhead occurs when the RTL file is being built during which the same signals have to be listed at different places within the list. For example, a port list might list signals a, b, and c as they are coming in and then in the input/output list, the same signals a, b, and c might be listed as pins coming out. Some of the redundant information includes declaring the type and sizes of signals used in the design, sensitivity lists for constructs such as state machines and case statements, port lists which are the same as the input/output declarations, and module file instantiations. Moreover, such redundant information was previously entered manually, and such maintenance consumes large portions of an individual's time.
As a result, there is a need to eliminate the creation of such redundant information manually in order to reduce the overhead involved with respect to an individual's time.